ASIC / FPGA Design Engineer(RTL Design & Verification)

Job Title: ASIC / FPGA Design Engineer (RTL Design & Verification)

Location: Remote / Work From Home

Shift: General Shift
Compensation: Market Standard

Experience:2-15yrs

Role Overview

We are looking for talented engineers with experience in ASIC and/or FPGA development. The ideal candidate will have a strong foundation in RTL design, design verification, and digital architecture, and the ability to work independently in a fast-paced environment.

Key Responsibilities

• Design, implement, and verify RTL modules using SystemVerilog / Verilog
• Develop and modify hardware IP (including open-source designs) into structured engineering assignments
• Create practical, industry-relevant problem statements aligned with real-world use cases
• Debug and analyze module-level and SoC-level hardware behavior
• Work autonomously with minimal supervision in a dynamic setup

Required Skills & Qualifications

• Strong coding proficiency in SystemVerilog / Verilog (mandatory)
• Hands-on experience in RTL design and/or RTL verification
• Solid understanding of:
• Digital design fundamentals
• Simulation flows
• Verification methodologies
• Ability to clearly explain low-level hardware concepts to non-hardware stakeholders
• Strong written and verbal communication skills in English

Nice to Have

• Experience contributing to production ASIC chips
• Familiarity with AI/LLM tools such as ChatGPT, GitHub Copilot, or Claude
• Prior experience in startups or high-growth engineering environments

Pay: ₹1,000,000.00 - ₹3,000,000.00 per year

Benefits:

• Paid sick time
• Paid time off

Experience:

• Strong coding proficiency in SystemVerilog / Verilog : 2 years (Required)
• RTL design and RTL verification: 2 years (Required)

Work Location: Remote